The development of semiconductor switching technology for high power applications in motor drive circuits, appliance controls and lighting ballasts, for example, began with the bipolar junction transistor. As the technology matured, bipolar devices became capable of handling large current densities in the range of 40-50 A/cm.sup.2, with blocking voltages of 600 V.
Despite the attractive power ratings achieved by bipolar transistors, there exist several fundamental drawbacks to the suitability of bipolar transistors for all high power applications. First of all, bipolar transistors are current controlled devices. For example, a large control current into the base, typically one fifth to one tenth of the collector current, is required to maintain the device in an operating mode. Even larger base currents, however, are required for high speed forced turn-off. These characteristics make the base drive circuitry complex and expensive. The bipolar transistor is also vulnerable to breakdown if a high current and high voltage are simultaneously applied to the device, as commonly required in inductive power circuit applications, for example. Furthermore, it is difficult to parallel connect these devices since current diversion to a single device occurs at high temperatures, making emitter ballasting schemes necessary.
The power MOSFET was developed to address this base drive problem. In a power MOSFET, a gate electrode bias is applied for turn-on and turn-off control. Turn-on occurs when a conductive channel is formed between the MOSFET's source and drain regions under appropriate bias. The gate electrode is separated from the device's active area by an intervening insulator, typically silicon dioxide. Because the gate is insulated from the active area, little if any gate current is required in either the on-state or off-state. The gate current is also kept small during switching because the gate forms a capacitor with the device's active area. Thus, only charging and discharging current ("displacement current") is required. The high input impedance of the gate, caused by the insulator, is a primary feature of the power MOSFET. Moreover, because of the minimal current demands on the gate, the gate drive circuitry and devices can be easily implemented on a single chip. As compared to bipolar technology, the simple gate control provides for a large reduction in cost and a significant improvement in reliability.
These benefits are offset, however, by the high on-resistance of the MOSFET's active region, which arises from the absence of minority carrier injection. As a result, the device's operating forward current density is limited to relatively low values, typically in the range of 10 A/cm.sup.2 for a 600 V device, as compared to 40-50 A/cm.sup.2 for the bipolar transistor.
On the basis of these features of power bipolar transistors and MOSFET devices, hybrid devices embodying a combination of bipolar current conduction with MOS-controlled current flow were developed and, found to provide significant advantages over single technologies such as bipolar or MOSFET alone. Classes of such hybrid devices include various types of MOS-gated thyristors as well as the insulated gate bipolar transistor (IGBT), also commonly referred to by the acronyms COMFET (Conductivity-Modulated FET) and BIFET (Bipolar-mode MOSFET).
For example, in the insulated gate bipolar transistor (IGBT), disclosed in an article by inventor B. J. Baliga, and M. S. Adler, R. P. Love, P. V. Gray and N. Zommer, entitled "The Insulated Gate Transistor: A New Three terminal MOS Controlled Bipolar Power Device." IEEE Trans. Electron Devices, ED-31, pp. 821-828 (1984), on-state losses were shown to be greatly reduced when compared to power MOSFETs. This was caused by the conductivity modulation of the IGBT's drift region during the on-state. In addition, very high conduction current densities in the range of 200-300 A/cm.sup.2 can also be achieved. Accordingly, IGBTs were shown to have a conduction current density approximately 20 times that of equivalently-sized power MOSFETs and five (5) times that of equivalently-sized bipolar transistors. Typical turn-off times for the IGBT were also shown to be in the range of 10-50 .mu.s. A cross-sectional representation of an insulated gate bipolar transistor with 600 volt blocking capability fabricated using a vertical DMOS process is shown in FIG. 1. FIG. 1 is a reproduction of FIG. 1 from the aforesaid Baliga, et al. article.
The operation of the IGBT can be described as follows with respect to the electrical schematic and I-V characteristics shown in FIGS. 1 and 2, respectively. In the reverse bias region, the anode is biased negative with respect to the cathode and the lower junction (J3) is reversed biased, thereby preventing conduction from the cathode to anode even though the upper junction (J2) is forward biased. This provides the device with its reverse blocking capability.
In its forward blocking state when the anode is biased positive with respect to the cathode and the gate and cathode are electrically connected, the upper junction (J2) is reversed biased and conduction is prevented. If, however, a positive gate bias of sufficient magnitude is applied to the gate, the P-base region under the gate becomes inverted and the device operates in its forward conducting mode as shown by the I-V characteristics on the right hand side of FIG. 2. In this mode of operation, electrons flow from the N.sup.+ source region into the N-base region via the channel (inversion layer) under the gate. In addition, the lower junction (J3) is forward biased and the substrate P.sup.+ region injects holes (minority carriers) into the N-base region. As the forward bias increases, the injected hole concentration increases until it exceeds the background doping level of the N-base. This high level minority carrier injection causes a conductivity modulation in the N-base and significantly reduces the IGBT's on-resistance.
As long as the gate bias is sufficiently large to produce enough charge in the inversion layer, the IGBT forward conduction characteristics will resemble those of a P-i-N diode, i.e., will follow the vertical portion of the I-V curves shown in FIG. 2. If the inversion layer conductivity is low, however, a substantial voltage drop across the channel will occur. This mode of operation represents the saturation region shown by the horizontal portions of the I-V curves in FIG. 2. As shown, higher gate voltages result in higher saturation current densities.
To switch the IGBT from its forward conducting mode of operation to its reverse blocking mode requires the removal of the positive gate bias to thereby cut off the supply of electrons from the N.sup.+ source region to the N-base region. Because of the high minority carrier concentration in the N-base region, turn-off of the IGBT is not immediate, but instead is dependent on the minority carrier recombination lifetime in the N-base region. Accordingly, the IGBT offers the potential for high forward conduction current density, full gate controlled transistor operation, low gate drive power requirements and reverse blocking capability providing directional power flow control.
One significant drawback to the operation of IGBTs at high current densities is the presence of the parasitic P-N-P-N structure between the anode and cathode which can cause a loss in the gate controlled turn-off capability. For example, the equivalent circuit for the IGBT shown schematically in FIG. 1 indicates the presence of a regenerative P-N-P-N path that can latch up if the lateral current in the P-base is sufficient to forward bias the P-base/N.sup.+ source junction. As will be understood by one skilled in the art, latch-up can be prevented so long as the sum of the current gains of the regeneratively coupled P-N-P and N-P-N transistors (.alpha..sub.pnp, .alpha..sub.npn) is less than unity.
The shorting resistance R.sub.s in FIG. 1 represents the short circuit resistance between the base (P-base) and emitter (N.sup.+ source) of the N-P-N transistor. The magnitude of R.sub.s is determined by the resistance of the P-base region and the distance between the edge of the N.sup.+ source region at point A and its contact point at point B. Because the current gain of the N-P-N transistor (.alpha..sub.npn) is directly dependent on the magnitude of R.sub.s, a small R.sub.s has been deemed essential for latch-up free operation at high forward current densities. When the P-base sheet resistance is kept low and/or the width of the N.sup.+ source region is kept small, electron injection from the N.sup.+ source region to the P-base can be suppressed because the uppermost P-N junction between the P-base and N.sup.+ source is effectively short circuited, thereby eliminating the regenerative P-N-P-N path from between the anode and cathode.
However, as described in an article by J. P Russell, A. M. Goodman, L. A. Goodman and J. M. Neilson, entitled "The COMFET-A New High Conductance MOS-Gated Device", IEEE Electron Device Letters, Vol EDL-4, No. 3, March (1983), pp. 63-65, even devices having a relatively low R.sub.s can be susceptible to latch-up if sufficiently large forward current densities cause significant emitter injection into the base of the N-P-N transistor and cause .alpha..sub.npn to increase. To reduce the likelihood of parasitic latch-up, the COMFET structure was modified to include a heavily doped P.sup.+ region in the middle of the P-base region, electrically connected to the cathode contact. To further lessen the magnitude of R.sub.s, an aluminum contact was also provided for shorting the N.sup.+ source regions to the P-base region.
Other attempts have also be made to reduce the IGBT's susceptibility to latch-up. For example, in an article by A. M. Goodman, J. P. Russell, L. A. Goodman, C. J. Nuese and J. M. Neilson, entitled "Improved COMFETs with Fast Switching Speed and High-Current Capability", IEEE International Electron Devices Meeting Digest, Abstract 4.3, (1983), pp. 79-82, a highly doped (N.sup.+) epitaxial layer was formed on top of the P.sup.+ anode region at junction J3 in order to lower the gain of the lower P-N-P transistor (.alpha..sub.pnp) and thereby reduce the likelihood of parasitic latch-up at high current densities.
A hole-bypass technique involving the elimination of one of the two uppermost N-type source regions from the uppermost P-base region is also described in an article by A. Nakagawa, H. Ohashi, M. Kurata, H. Yamaguchi and K. Watanabe, entitled "Non-Latch-Up 1200 v 75A Bipolar-Mode MOSFET with Large ASO" IEEE International Electron Devices Meeting Digest, Abstract 16.8, (1984), pp. 860-861. By eliminating the source region on one side of the P-base, the hole current collected by the base on that side is provided to the cathode contact without having to travel around the N.sup.+ source region. This bypass technique reduces the likelihood that the uppermost P-N junction between the P-base and N.sup.+ source will become forward biased at high current densities.
Notwithstanding these attempts to limit the susceptibility to sustained parasitic thyristor latchup, the presence of the N.sup.+ source region in the P-base poses a risk that under certain operating conditions parasitic latch-up will occur.